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A Novel Architecture and Routing Algorithm for Dynamic Reconfigurable Network-on-Chip.

, , and . ISPA, page 177-182. IEEE Computer Society, (2011)

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Message scheduling and timing analysis for flexray dynamic segment by considering slot-multiplexing., , and . ICVES, page 56-61. IEEE, (2015)A 28Gbps 4×4 switch with low jitter SerDes using area-saving RF model in 0.13µm CMOS technology., , , , , , , , , and 1 other author(s). ISCAS, page 3086-3089. IEEE, (2008)Cluster-Based CAN with Enhanced Transmission Capability for Vehicle Networks., , , and . ICCVE, page 43-48. IEEE Computer Society, (2012)Are We Providing the Right Education for Computer Science/Engineering Students?, , , , , and . ICPADS, page 14-15. IEEE Computer Society, (1994)Achieving Global Fairness for On-Chip Network Using Group Allocation., , and . IPDPS Workshops, page 930-937. IEEE Computer Society, (2012)A Novel Architecture and Routing Algorithm for Dynamic Reconfigurable Network-on-Chip., , and . ISPA, page 177-182. IEEE Computer Society, (2011)An 8 × 8 20 Gbps Reconfigurable Load Balanced TDM Switch IC for High-Speed Networking., , , , , , , , , and 2 other author(s). J. Signal Process. Syst., 66 (1): 57-73 (2012)Performance Evaluation of a Parallel I/O Architecture., , and . International Conference on Supercomputing, page 404-413. ACM, (1995)Efficient Stack Simulation for Set-Associative Virtual Address Cache with Real Tags., , and . IEEE Trans. Computers, 44 (5): 719-723 (1995)The Effects of Network Delays on the Performance of MIN-Based Cache Coherence Protocols., and . ICPP (1), page 292-295. CRC Press, (1991)