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A 4.2-mW 10-MHz BW 74.4-dB SNDR Continuous-Time Delta-Sigma Modulator With SAR-Assisted Digital-Domain Noise Coupling., , , , , , , , and . IEEE J. Solid State Circuits, 53 (4): 1139-1148 (2018)A 14mW Multi-bit ΔΣ Modulator with 82dB SNR and 86dB DR for ADSL2+., and . ISSCC, page 161-170. IEEE, (2006)A High-Speed Delta-Sigma Modulator with Relaxed DEM Timing Requirement., and . ISCAS, page 733-736. IEEE, (2007)A 630μW zero-crossing-based ΔΣ ADC using switched-resistor current sources in 45nm CMOS., , , , and . CICC, page 1-4. IEEE, (2009)A Power-Efficient Two-Channel Time-Interleaved ΣΔ Modulator for Broadband Applications., , and . IEEE J. Solid State Circuits, 42 (6): 1206-1215 (2007)A 2.4ps resolution 2.1mW second-order noise-shaped time-to-digital converter with 3.2ns range in 1MHz bandwidth., , , and . CICC, page 1-4. IEEE, (2010)A continuous-time input pipeline ADC with inherent anti-alias filtering., , , , and . CICC, page 275-278. IEEE, (2009)Mixed-Order Sturdy MASH Delta-Sigma Modulator., , , and . ISCAS, page 257-260. IEEE, (2007)A 5.4mW 2-Channel Time-Interleaved Multi-bit ΔΣ Modulator with 80dB SNR and 85dB DR for ADSL., , and . ISSCC, page 171-180. IEEE, (2006)An 11mW 100MHz 16X-OSR 64dB-SNDR hybrid CT/DT ΔΣ ADC with relaxed DEM timing., , , , , , , and . CICC, page 171-174. IEEE, (2009)