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Disambiguation of "Vinet, Maud"

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Towards scalable silicon quantum computing.

, , , , , , , , , , , , , , , , and . DRC, page 1-2. IEEE, (2018)

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Maud Lampe

Jaime Vinet

Maud Koch

Maud Fuhrmann

Maud Curling

 

Other publications of authors with the same name

3D monolithic integration., , , , , , , , , and 6 other author(s). ISCAS, page 2233-2236. IEEE, (2011)System on Wafer: A New Silicon Concept in SiP., , , , , , , , , and . Proc. IEEE, 97 (1): 60-69 (2009)Experimental Assessment of Variability in Junctionless Nanowire nMOS Transistors., , , , , and . ESSDERC, page 223-226. IEEE, (2021)Coupling control in the few-electron regime of quantum dot arrays using 2-metal gate levels in CMOS technology., , , , , , , , , and 6 other author(s). ESSCIRC, page 45-48. IEEE, (2022)Si MOS technology for spin-based quantum computing., , , , , , , , , and 7 other author(s). ESSDERC, page 12-17. IEEE, (2018)Opportunities brought by sequential 3D CoolCube™ integration., , , , , , , , , and 11 other author(s). ESSDERC, page 226-229. IEEE, (2016)The Coupled Atom Transistor: A first realization with shallow donors implanted in a FDSOI silicon nanowire., , , , , , , , , and 2 other author(s). ESSDERC, page 147-150. IEEE, (2013)Guidelines for intermediate back end of line (BEOL) for 3D sequential integration., , , , , , , , , and 18 other author(s). ESSDERC, page 252-255. IEEE, (2017)FDSOI bottom MOSFETs stability versus top transistor thermal budget featuring 3D monolithic integration., , , , , , , , , and 6 other author(s). ESSDERC, page 110-113. IEEE, (2014)Fast Measurement of BTI on 28nm Fully Depleted Silicon-On-Insulator MOSFETs at Cryogenic Temperature down to 4K., , , , , , , , , and . IRPS, page 7. IEEE, (2022)