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An All-Digital True-Random-Number Generator with Integrated De-correlation and Bias Correction at 3.2-to-86 MB/S, 2.58 PJ/Bit in 65-NM CMOS., , , , , и . VLSI Circuits, стр. 1-2. IEEE, (2018)A 32nm fully integrated reconfigurable switched-capacitor DC-DC converter delivering 0.55W/mm2 at 81% efficiency., , , , , и . ISSCC, стр. 210-211. IEEE, (2010)Architecture Considerations for Stochastic Computing Accelerators., , , , , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 37 (11): 2277-2289 (2018)Computationally Enabled Minimum Total Energy Tracking for a Performance Regulated Sub-Threshold Microprocessor in 65-nm CMOS., , и . IEEE J. Solid State Circuits, 55 (2): 494-504 (2020)187 MHz Subthreshold-Supply Charge-Recovery FIR., , , и . IEEE J. Solid State Circuits, 45 (4): 793-803 (2010)Resonant clock design for a power-efficient high-volume x86-64 microprocessor., , , , , и . ISSCC, стр. 68-70. IEEE, (2012)A 0.8-1.2GHz Single-Phase Resonant-Clocked FIR Filter with Level-Sensitive Latches., , и . CICC, стр. 583-586. IEEE, (2007)Energy-Efficient Low-Latency 600 MHz FIR With High-Overdrive Charge-Recovery Logic., , , и . IEEE Trans. Very Large Scale Integr. Syst., 20 (6): 977-988 (2012)A Unified Clock and Switched-Capacitor-Based Power Delivery Architecture for Variation Tolerance in Low-Voltage SoC Domains., , , , , , , и . IEEE J. Solid State Circuits, 54 (4): 1173-1184 (2019)Resonant-Clock Latch-Based Design., , и . IEEE J. Solid State Circuits, 43 (4): 864-873 (2008)