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Optimal clock period FPGA technology mapping for sequential circuits.

, and . ACM Trans. Design Autom. Electr. Syst., 3 (3): 437-462 (1998)

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Register allocation for data flow graphs with conditional branches and loops., , and . EURO-DAC, page 232-237. IEEE Computer Society, (1993)Algorithms for permutation channel routing., and . Integr., 5 (1): 17-45 (1987)Complementary sets of sequences., and . IEEE Trans. Inf. Theory, 18 (5): 644-652 (1972)On a Class of Scheduling Algorithms for Multiprocessors Computing Systems., and . Sagamore Computer Conference, volume 24 of Lecture Notes in Computer Science, page 1-16. Springer, (1974)SS/TDMA Time Slot Assignment with Restricted Switching Modes., , and . IEEE Trans. Commun., 31 (1): 149-154 (1983)Domino logic synthesis based on implication graph., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 21 (2): 232-240 (2002)Timing-driven placement for regular architectures., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 16 (6): 597-608 (1997)Area minimization for floorplans., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 14 (1): 123-132 (1995)Optimization of the maximum delay of global interconnects duringlayer assignment., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 20 (4): 503-515 (2001)Minimum crosstalk channel routing., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 15 (5): 465-474 (1996)