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Performance-driven register write inhibition in high-level synthesis under strict maximum-permissible clock latency range., и . ASP-DAC, стр. 239-244. IEEE, (2012)A Linear Programming Model for Power Flow Control Problem Considering Controllable and Fluctuating Power Devices., , и . GCCE, стр. 96-99. IEEE, (2019)Statistical Analysis Driven Synthesis of Application Specific Asynchronous Systems., и . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 90-A (3): 659-669 (2007)Two-Graph Approach to Temperature Dependent Skew Scheduling.. ISQED, стр. 432-437. IEEE, (2020)Post-silicon skew tuning algorithm utilizing setup and hold timing tests., и . ISCAS, стр. 125-128. IEEE, (2012)Register binding and domain assignment for multi-domain clock skew scheduling-aware high-level synthesis., и . ISQED, стр. 778-783. IEEE, (2012)Optimal register assignment with minimum-delay compensation for latch-based design., и . APCCAS, стр. 887-890. IEEE, (2010)Automated selection of check variables for area-efficient soft-error tolerant datapath synthesis., и . ISCAS, стр. 49-52. IEEE, (2015)Characterization and computation of Steiner wiring based on Elmore's delay model., и . APCCAS (2), стр. 335-340. IEEE, (2002)Assignment-Driven Loop Pipeline Scheduling and Its Application to Data-Path Synthesis., , и . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 85-A (4): 819-826 (2002)