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Two-level compression through selective reseeding.

, , , , , и . ITC, стр. 1-10. IEEE Computer Society, (2013)

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Jonathon Howard

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Другие публикации лиц с тем же именем

Enhancing testability by structured partial scan., , и . VTS, стр. 152-157. IEEE Computer Society, (2012)Hybrid selector for high-X scan compression., , , и . ITC, стр. 1-10. IEEE Computer Society, (2012)Optimizing Memory Tests by Analyzing Defect Coverage., , , и . MTDT, стр. 20-28. IEEE Computer Society, (2000)XLBIST: X-Tolerant Logic BIST., , , и . ITC, стр. 1-9. IEEE, (2018)An Efficient Supervised Learning Method to Predict Power Supply Noise During At-speed Test., , , , , , и . ITC, стр. 1-10. IEEE, (2019)Innovative practices session 10C: Delay test., , , и . VTS, стр. 1. IEEE Computer Society, (2013)Determining Redundancy Requirements for Memory Arrays with Critical Area Analysis., , , , , и . MTDT, стр. 48-53. IEEE Computer Society, (1999)Innovative practices session 6C: Latest practices in test compression., , , и . VTS, стр. 1. IEEE Computer Society, (2013)Two-level compression through selective reseeding., , , , , и . ITC, стр. 1-10. IEEE Computer Society, (2013)Achieving extreme scan compression for SoC Designs., , , и . ITC, стр. 1-8. IEEE Computer Society, (2014)