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On-line Fault Detection and Location for NoC Interconnects.

, , , , and . IOLTS, page 145-150. IEEE Computer Society, (2006)

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A parity-preserving multi-input signature analyzer and its application for concurrent checking and BIST., and . J. Electron. Test., 8 (2): 165-177 (1996)A linear code-preserving signature analyzer COPMISR., , and . VTS, page 350-355. IEEE Computer Society, (1997)A new method for correcting time and soft errors in combinational circuits., , and . DDECS, page 283-286. IEEE Computer Society, (2013)Self-Checking Comparator with One Periodic Output., , , and . IEEE Trans. Computers, 45 (3): 379-380 (1996)A New Code-Disjoint Sum-Bit Duplicated Carry Look-Ahead Adder for Parity Codes., , and . Asian Test Symposium, page 365-. IEEE Computer Society, (2001)Code-Disjoint Carry-Dependent Sum Adder with Partial Look-Ahead., , and . IOLTW, page 147-152. IEEE Computer Society, (2001)Design of Self-Parity Combinational Circuits for Self-testing and On-line Detection., and . DFT, page 239-246. IEEE Computer Society, (1993)Concurrently self-testing embedded checkers for ultra-reliable fault-tolerant systems., and . VTS, page 138-144. IEEE Computer Society, (1996)A Multi-Mode Scannable Memory Element for High Test Application Efficiency and Delay Testing., , and . VTS, page 324-331. IEEE Computer Society, (1998)Code-Disjoint Circuits for Parity Circuits., , and . Asian Test Symposium, page 100-. IEEE Computer Society, (1997)