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A Discrete-Time Input Delta Sigma ADC Architecture Using a Dual-VCO-Based Integrator., , и . IEEE Trans. Circuits Syst. II Express Briefs, 57-II (11): 848-852 (2010)A Unity-Gain Buffer with Reduced Offset and Gain Error., , и . CICC, стр. 825-828. IEEE, (2006)Level-Crossing Detection based Low-Power Sigma-Delta ADC for Sensor Applications., , , и . MWSCAS, стр. 663-666. IEEE, (2020)Efficient 6-bit A/D converter using a 1-bit folding front end., , и . IEEE J. Solid State Circuits, 34 (8): 1056-1062 (1999)A 1.1mW, 63.7dB-SNDR, 10MHz-BW hybrid voltage -time domain ADC., , и . MWSCAS, стр. 1053-1056. IEEE, (2014)Analog signal processing in deep submicron CMOS technologies using inverters., , и . MWSCAS, стр. 394-397. IEEE, (2014)Clock-gated harmonic rejection mixers., и . CICC, стр. 1-8. IEEE, (2012)A hybrid SAR-VCO ΔΣ ADC with first-order noise shaping., , , , , и . CICC, стр. 1-4. IEEE, (2014)An uncalibrated 2MHz, 6mW, 63.5dB SNDR discrete-time input VCO-based ΔΣ ADC., , и . CICC, стр. 1-4. IEEE, (2012)Operational current to frequency converter., , , , и . MWSCAS, стр. 900-903. IEEE, (2013)