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Disambiguation of "Hunter, Hillery C."

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Hardware-compiler co-design for adjustable data power savings.

, , , and . Microprocess. Microsystems, 33 (4): 244-253 (2009)

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Julia Hunter

Hunter Rouse

Charles Hunter

Regina Hunter

Aleksandra Hunter

 

Other publications of authors with the same name

BlueConnect: Decomposing all-reduce for deep learning on heterogeneous network hierarchy., , , , and . IBM J. Res. Dev., 63 (6): 1:1-1:11 (2019)A 1 MB Cache Subsystem Prototype With 1.8 ns Embedded DRAMs in 45 nm SOI CMOS., , , , , , , , , and 11 other author(s). IEEE J. Solid State Circuits, 44 (4): 1216-1226 (2009)The virtual write queue: coordinating DRAM and last-level cache policies., , , , and . ISCA, page 72-82. ACM, (2010)Hardware Support for Dynamic Management of Compiler-Directed Computation Reuse., , , and . ASPLOS, page 222-233. ACM Press, (2000)BlueConnect: Decomposing All-Reduce for Deep Learning on Heterogeneous Network Hierarchy., , , and . SysML, mlsys.org, (2019)An innovative low-power high-performance programmable signal processor for digital communications., , , , , , , , , and 6 other author(s). IBM J. Res. Dev., 47 (2-3): 299-326 (2003)PANEL: Open panel and discussion on tackling complexity, reproducibility and tech transfer challenges in a rapidly evolving AI/ML/systems research., , , , , and . ReQuEST@ASPLOS, page 7. ACM, (2018)Guest Editorial Computing in Emerging Technologies (Second Issue)., , , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 5 (1): 1-4 (2015)Code coverage and input variability: effects on architecture and compiler research., and . CASES, page 79-87. ACM, (2002)A 500 MHz Random Cycle, 1.5 ns Latency, SOI Embedded DRAM Macro Featuring a Three-Transistor Micro Sense Amplifier., , , , , , , , , and 7 other author(s). IEEE J. Solid State Circuits, 43 (1): 86-95 (2008)