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Disambiguation of "Moon, Yongsam"

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Presetting pulse-based flip-flop.

, , , , and . ISCAS, page 588-591. IEEE, (2008)

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In-Hyung Moon

Philipp Moon

Baesu Moon

Oveeyen Moonian

Sangbok Moon

 

Other publications of authors with the same name

Presetting pulse-based flip-flop., , , , and . ISCAS, page 588-591. IEEE, (2008)Signal detector for 6-Gbps 55-nm CMOS Serial ATA receiver.. IEICE Electron. Express, 13 (9): 20160286 (2016)An all-analog multiphase delay-locked loop using a replica delay line for wide-range operation and low-jitter performance., , , , and . IEEE J. Solid State Circuits, 35 (3): 377-384 (2000)1.2V 1.6Gb/s 56nm 6F2 4Gb DDR3 SDRAM with hybrid-I/O sense amplifier and segmented sub-array architecture., , , , , , , , , and 5 other author(s). ISSCC, page 128-129. IEEE, (2009)A 5-Gb/s 0.25-μm CMOS jitter-tolerant variable-interval oversampling clock/data recovery circuit., , , , , , , , , and . IEEE J. Solid State Circuits, 37 (12): 1822-1830 (2002)A Quad 6Gb/s Multi-rate CMOS Transceiver with TX Rise/Fall-Time Control., , , , and . ISSCC, page 233-242. IEEE, (2006)A quad 0.6-3.2 Gb/s/channel interference-free CMOS transceiver for backplane serial link., , , , , and . IEEE J. Solid State Circuits, 39 (5): 795-803 (2004)A 960-Mb/s/pin interface for skew-tolerant bus using low jitter PLL., , , , , and . IEEE J. Solid State Circuits, 32 (5): 691-700 (1997)A 62.5-250 MHz multi-phase delay-locked loop using a replica delay line with triply controlled delay cells., , , , and . CICC, page 299-302. IEEE, (1999)A spread-spectrum clock generator for 6-Gbps Serial ATA transceiver.. IEICE Electron. Express, 7 (13): 931-935 (2010)