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Disambiguation of "Saluja, Kewal K."

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A new approach to the design of built-in self-testing PLAs for high fault coverage.

, and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 7 (1): 60-67 (1988)

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Heinz Kewald

Kewal Krishen Mehta

Aman K K Bhasin

K Schweizerhof

K Schaber

 

Other publications of authors with the same name

A Data Compression Technique for Built-In Self-Test., , and . IEEE Trans. Computers, 37 (9): 1151-1156 (1988)Correction: IEEE Transactions on Computers 38(2): 320 (1989).Modeling Detection Latency with Collaborative Mobile Sensing Architecture., , and . IEEE Trans. Computers, 58 (5): 692-705 (2009)Hypergraph Coloring and Reconfigured RAM Testing., and . IEEE Trans. Computers, 43 (6): 725-736 (1994)Instruction-based delay fault self-testing of pipelined processor cores., , , and . ISCAS (6), page 5686-5689. IEEE, (2005)Analysis and test procedures for NOR flash memory defects., and . Microelectron. Reliab., 48 (5): 698-709 (2008)Routing TCP Flows in Underwater Mesh Networks., , and . IEEE J. Sel. Areas Commun., 29 (10): 2022-2032 (2011)Test Generation for Delay Faults on Clock Lines under Launch-on-Capture Test Environment., , , and . IEICE Trans. Inf. Syst., 96-D (6): 1323-1331 (2013)Delay Fault Testing of Processor Cores in Functional Mode., , , and . IEICE Trans. Inf. Syst., 88-D (3): 610-618 (2005)Fault Simulation and Test Generation for Transistor Shorts Using Stuck-at Test Tools., , , , and . IEICE Trans. Inf. Syst., 91-D (3): 690-699 (2008)Efficient Test Set Modification for Capture Power Reduction., , , , , , and . J. Low Power Electron., 1 (3): 319-330 (2005)