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Disambiguation of "Lee, Hanho"

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A Discrepancy-Computationless RiBM algorithm and its architecture for BCH decoders.

, and . SoCC, page 379-382. IEEE, (2008)

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Hanho Jeon

Bernhard Hanhoff

Heike Hanhörster

Heinrich Hanholz

Ingrid Hanhoff

 

Other publications of authors with the same name

A High-Speed Two-Parallel Radix-24 FFT/IFFT Processor for MB-OFDM UWB Systems., and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 91-A (4): 1206-1211 (2008)A Self-Reconfigurable Adaptive FIR Filter System on Partial Reconfiguration Platform., and . IEICE Trans. Inf. Syst., 90-D (12): 1932-1938 (2007)Two-Extra-Column Trellis Min-Max Decoder Architecture for Nonbinary LDPC Codes., and . IEEE Trans. Very Large Scale Integr. Syst., 25 (5): 1787-1791 (2017)Block-Circulant RS-LDPC Code: Code Construction and Efficient Decoder Design., and . IEEE Trans. Very Large Scale Integr. Syst., 21 (7): 1337-1341 (2013)High-performance iterative BCH decoder architecture for 100 Gb/s optical communications., and . ISCAS, page 1344-1347. IEEE, (2013)Low-cost variable-length FFT processor for DVB-T/H applications., and . APCCAS, page 752-755. IEEE, (2010)Two bit-level pipelined viterbi decoder for high-performance UWB applications., and . ISCAS, page 1012-1015. IEEE, (2008)Parallel architecture for concatenated polar-CRC codes., and . ISOCC, page 173-174. IEEE, (2017)Area-Efficient Number Theoretic Transform Architecture for Homomorphic Encryption., , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 70 (3): 1270-1283 (March 2023)Hamming-Distance Trellis Min-Max-Based Architecture for Non-Binary LDPC Decoder., , and . IEEE Trans. Circuits Syst. II Express Briefs, 70 (7): 2390-2394 (July 2023)