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Data Parallel Code Generation for Arbitrarily Tiled Loop Nests., , , and . PDPTA, page 610-616. CSREA Press, (2002)LCA: a memory link and cache-aware co-scheduling approach for CMPs., , , , , and . PACT, page 469-470. ACM, (2014)An efficient and fair scheduling policy for multiprocessor platforms., , , , and . ISCAS, page 1-4. IEEE, (2017)Performance evaluation of the sparse matrix-vector multiplication on modern architectures., , , , and . J. Supercomput., 50 (1): 36-77 (2009)Architectural Support for Efficient Data Movement in Disaggregated Systems., , , , , , and . CoRR, (2023)Enhancing and Exploiting Contiguity for Fast Memory Virtualization., , , , , , and . ISCA, page 515-528. IEEE, (2020)Towards Efficient Sparse Matrix Vector Multiplication on Real Processing-In-Memory Architectures., , , , , and . SIGMETRICS (Abstracts), page 33-34. ACM, (2022)Architectural Support for Efficient Data Movement in Fully Disaggregated Systems., , , , , , and . SIGMETRICS (Abstracts), page 5-6. ACM, (2023)Massively Concurrent Red-Black Trees with Hardware Transactional Memory., , , and . PDP, page 127-134. IEEE Computer Society, (2016)Selecting the tile shape to reduce the total communication volume., , and . IPDPS, IEEE, (2006)