( en | de | ru )

 

Disambiguation of "Miwa, Shinobu"

Author of the publication

copydeleteadd this publication to your clipboard
D-MRAM cache: enhancing energy efficiency with 3T-1MTJ DRAM/MRAM hybrid memory.

, , , , , , , , and . DATE, page 1813-1818. EDA Consortium San Jose, CA, USA / ACM DL, (2013)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

No persons found for author name Miwa, Shinobu
add a person with the name Miwa, Shinobu
 

Other publications of authors with the same name

PredCom: A Predictive Approach to Collecting Approximated Communication Traces., , and . IEEE Trans. Parallel Distributed Syst., 32 (1): 45-58 (2021)Multi-Level Packet Processing Caches., , , and . COOL CHIPS, page 1-3. IEEE, (2019)Evaluation of Core Hopping on POWER7., and . SIGMETRICS Perform. Evaluation Rev., 42 (3): 55-60 (2014)Functionally-Predefined Kernel: a Way to Reduce CNN Computation., , , and . PACRIM, page 1-6. IEEE, (2019)Footprint-Based DIMM Hotplug., , , , and . IEEE Trans. Computers, 69 (2): 172-184 (2020)CNFET7: An Open Source Cell Library for 7-nm CNFET Technology., , , , , and . ASP-DAC, page 763-768. ACM, (2023)Normally-off computing project: Challenges and opportunities., , and . ASP-DAC, page 1-5. IEEE, (2014)Data-aware power management for periodic real-time systems with non-volatile memory., , , , , , , , and . NVMSA, page 1-6. IEEE, (2014)Initial Study of Reconfigurable Neural Network Accelerators., , , , , and . CANDAR, page 707-709. IEEE Computer Society, (2016)McRouter: Multicast within a router for high performance network-on-chips., , , and . PACT, page 319-329. IEEE Computer Society, (2013)