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Width minimization in the Single-Electron Transistor array synthesis.

C. Liu, C. Chiang, C. Huang, C. Wang, Y. Chen, S. Datta, and V. Narayanan. DATE, page 1-4. European Design and Automation Association, (2014)

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P Narayanan

Hermine Narayanan

Vidya Narayanan

Narayanan Radhakrishnan

Narayanan Sundaram

Other publications of authors with the same name

Asymmetric Double-Gate Ferroelectric FET to Decouple the Tradeoff Between Thickness Scaling and Memory Window.Z. Jiang, Y. Xiao, S. Chatterjee, H. Mulaosmanovic, S. Dünkel, S. Soss, S. Beyer, R. Joshi, Y. Chauhan, H. Amrouch and 2 other author(s). VLSI Technology and Circuits, page 395-396. IEEE, (2022)FeFET-based low-power bitwise logic-in-memory with direct write-back and data-adaptive dynamic sensing interface.M. Lee, W. Tang, B. Xue, J. Wu, M. Ma, Y. Wang, Y. Liu, D. Fan, V. Narayanan, H. Yang and 1 other author(s). ISLPED, page 127-132. ACM, (2020)Design space for scaling-in general purpose computing within the DDR DRAM hierarchy for map-reduce workloads.S. Rai, A. Sivasubramaniam, A. Kumar, P. Rengasamy, V. Narayanan, A. Akel, and S. Eilert. CF, page 113-123. ACM, (2021)Communication-efficient k-Means for Edge-based Machine Learning.H. Lu, T. He, S. Wang, C. Liu, M. Mahdavi, V. Narayanan, K. Chan, and S. Pasteris. ICDCS, page 595-605. IEEE, (2020)Intelligent Vision Systems: Exploring the State-of-the-Art and Opportunities for the Future.S. Advani, S. Kestur, and V. Narayanan. iNIS, page 77-82. IEEE, (2015)Compiler-Directed Array Interleaving for Reducing Energy in Multi-Bank Memories.V. Delaluz, M. Kandemir, N. Vijaykrishnan, M. Irwin, A. Sivasubramaniam, and I. Kolcu. ASP-DAC/VLSI Design, page 288-. IEEE Computer Society, (2002)A case for heterogeneous on-chip interconnects for CMPs.A. Mishra, N. Vijaykrishnan, and C. Das. ISCA, page 389-400. ACM, (2011)GaaS-X: Graph Analytics Accelerator Supporting Sparse Data Representation using Crossbar Architectures.N. Challapalle, S. Rampalli, L. Song, N. Chandramoorthy, K. Swaminathan, J. Sampson, Y. Chen, and V. Narayanan. ISCA, page 433-445. IEEE, (2020)NEOFog: Nonvolatility-Exploiting Optimizations for Fog Computing.K. Ma, X. Li, M. Kandemir, J. Sampson, V. Narayanan, J. Li, T. Wu, Z. Wang, Y. Liu, and Y. Xie. ASPLOS, page 782-796. ACM, (2018)On the Detection of Clones in Sensor Networks Using Random Key Predistribution.R. Brooks, P. Govindaraju, M. Pirretti, N. Vijaykrishnan, and M. Kandemir. IEEE Trans. Syst. Man Cybern. Part C, 37 (6): 1246-1258 (2007)

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Width minimization in the Single-Electron Transistor array synthesis.

Please choose a person to relate this publication to

P Narayanan

Hermine Narayanan

Vidya Narayanan

Narayanan Radhakrishnan

Narayanan Sundaram

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Narayanan, Vijaykrishnan"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Width minimization in the Single-Electron Transistor array synthesis.

Please choose a person to relate this publication to

P Narayanan

Hermine Narayanan

Vidya Narayanan

Narayanan Radhakrishnan

Narayanan Sundaram

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
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APA
Chicago
DIN 1505
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MSOffice XML

Width minimization in the Single-Electron Transistor array synthesis.