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A Low-Energy Inductive Transceiver using Spike-Latency Encoding for Wireless 3D Integration., , and . ISLPED, page 1-6. IEEE, (2019)Run-time Detection and Mitigation of Power-Noise Viruses., , , and . IOLTS, page 275-280. IEEE, (2019)Design and Optimization of Inductive-Coupling Links for 3-D-ICs., , and . IEEE Trans. Very Large Scale Integr. Syst., 27 (3): 711-723 (2019)Circuit-aware architectural simulation., , , , , and . DAC, page 305-310. ACM, (2004)Razor: A Variability-Tolerant Design Methodology for Low-Power and Robust Computing.. University of Michigan, USA, (2009)Session 4 Overview: Processors Digital Architectures and Systems Subcommittee., , and . ISSCC, page 52-53. IEEE, (2021)Energy-efficient approximate wallace-tree multiplier using significance-driven logic compression., , , , , and . SiPS, page 1-6. IEEE, (2017)Harnessing voltage margins for energy efficiency in multicore CPUs., , , , , and . MICRO, page 503-516. ACM, (2017)Modeling and characterization of the system-level Power Delivery Network for a dual-core ARM Cortex-A57 cluster in 28nm CMOS., , and . ISLPED, page 146-151. IEEE, (2015)Significance-Driven Logic Compression for Energy-Efficient Multiplier Design., , , , , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 8 (3): 417-430 (2018)