( en | de | ru )

 

Disambiguation of "Shin, Dongsuk"

Author of the publication

copydeleteadd this publication to your clipboard
A New Energy x Delay-Aware Flip-Flop.

, , , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 89-A (6): 1552-1557 (2006)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Dong-Shin Shin

Jeonghun Shin

Kirche als Weltforum: zum Dialogverständnis in kirchlichen Dokumenten seit dem Zweiten Vatikanischen Konzil. Uni München, (2009)

Hyeseon Shin

Koo Cheul Shin

Jung-Hyu Shin

 

Other publications of authors with the same name

A 7 ps Jitter 0.053 mm2 Fast Lock All-Digital DLL With a Wide Range and High Resolution DCC., , , and . IEEE J. Solid State Circuits, 44 (9): 2437-2451 (2009)Fully Automated Hardware-Driven Clock-Gating Architecture With Complete Clock Coverage for 4 nm Exynos Mobile SOC., , , , and . IEEE J. Solid State Circuits, 58 (1): 90-101 (2023)Wide frequency range duty cycle correction circuit for DDR interface., , and . IEICE Electron. Express, 5 (8): 254-259 (2008)Coverage expandable current type code controlled DCC with TDC-based range selector., , , , and . IEICE Electron. Express, 6 (5): 205-210 (2009)Erratum: Energy-efficient heterogeneous memory system for mobile platforms IEICE Electronics Express Vol. 14 (2017) No. 24 pp. 20171002., , and . IEICE Electron. Express, 15 (3): 20188001 (2018)A 0.17-1.4GHz low-jitter all digital DLL with TDC-based DCC using pulse width detection scheme., , , , , and . ESSCIRC, page 82-85. IEEE, (2008)A Fast-lock Synchronous Multi-phase Clock Generator based on a Time-to-digital Converter., , , , and . ISCAS, page 1-4. IEEE, (2009)A 4-bit 2GSamples/s parallel Flash ADC using comb-type reference ladder., , and . IEICE Electron. Express, 5 (15): 562-567 (2008)Bandwidth-aware DRAM page migration for heterogeneous mobile memory systems., and . ICCE, page 1-5. IEEE, (2018)A Low-Jitter Open-Loop All-Digital Clock Generator with 2 Cycle Lock-Time., , , , and . CICC, page 369-372. IEEE, (2007)