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Randomized Testing of RISC-V CPUs Using Direct Instruction Injection.

A. Joannou, P. Rugg, J. Woodruff, F. Fuchs, M. van der Maas, M. Naylor, M. Roe, R. Watson, P. Neumann, and S. Moore. IEEE Des. Test, 41 (1): 40-49 (February 2024)

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Rebecca Naylor

Matthew Mellon

Matthew David

Olumuyiwa Matthew

Peter Matthew

Other publications of authors with the same name

A Scoping Review Identifying the Need for Quality Research on the Use of Virtual Reality in Workplace Settings for Stress Management.M. Naylor, B. Ridout, and A. Campbell. Cyberpsychology Behav. Soc. Netw., 23 (8): 506-518 (2020)Managing the FPGA memory wall: Custom computing or vector processing?M. Naylor, P. Fox, A. Markettos, and S. Moore. FPL, page 1-6. IEEE, (2013)Termination detection for fine-grained message-passing architectures.M. Naylor, S. Moore, A. Mokhov, D. Thomas, J. Beaumont, S. Fleming, A. Markettos, T. Bytheway, and A. Brown. ASAP, page 17-24. IEEE, (2020)Rapid codesign of a soft vector processor and its compiler.M. Naylor, and S. Moore. FPL, page 1-4. IEEE, (2014)Randomized Testing of RISC-V CPUs Using Direct Instruction Injection.A. Joannou, P. Rugg, J. Woodruff, F. Fuchs, M. van der Maas, M. Naylor, M. Roe, R. Watson, P. Neumann, and S. Moore. IEEE Des. Test, 41 (1): 40-49 (February 2024)A spiking neural network on a portable FPGA tablet.M. Naylor, P. Fox, A. Markettos, and S. Moore. FPL, page 1. IEEE, (2013)Synchronization in graph analysis algorithms on the Partially Ordered Event-Triggered Systems many-core architecture.A. Rafiev, A. Yakovlev, G. Tarawneh, M. Naylor, S. Moore, D. Thomas, G. Bragg, M. Vousden, and A. Brown. IET Comput. Digit. Tech., 16 (2-3): 71-88 (2022)A generic synthesisable test bench.M. Naylor, and S. Moore. MEMOCODE, page 128-137. IEEE, (2015)A consistency checker for memory subsystem traces.M. Naylor, S. Moore, and A. Mujumdar. FMCAD, page 133-140. IEEE, (2016)POETS: An Event-driven Approach to Dissipative Particle Dynamics: Implementing a Massively Compute-intensive Problem on a Novel Hard/Software Architecture.A. Brown, J. Beaumont, D. Thomas, J. Shillcock, M. Naylor, G. Bragg, M. Vousden, S. Moore, and S. Fleming. ACM Trans. Parallel Comput., 10 (2): 7:1-7:32 (June 2023)

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Disambiguation of "Naylor, Matthew"

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Randomized Testing of RISC-V CPUs Using Direct Instruction Injection.

Please choose a person to relate this publication to

Rebecca Naylor

Matthew Mellon

Matthew David

Olumuyiwa Matthew

Peter Matthew

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Naylor, Matthew"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Randomized Testing of RISC-V CPUs Using Direct Instruction Injection.

Please choose a person to relate this publication to

Rebecca Naylor

Matthew Mellon

Matthew David

Olumuyiwa Matthew

Peter Matthew

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

Randomized Testing of RISC-V CPUs Using Direct Instruction Injection.