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Design of testing circuit and test generation for built-in current testing.

, , and . Syst. Comput. Jpn., 24 (5): 73-82 (1993)

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A Novel ATPG Method for Capture Power Reduction during Scan Testing., , , , , , and . IEICE Trans. Inf. Syst., 90-D (9): 1398-1405 (2007)Removal of Redundancy in Logic Circuits under Classification of Undetectable Faults., , and . FTCS, page 263-270. IEEE Computer Society, (1992)Design of testing circuit and test generation for built-in current testing., , and . Syst. Comput. Jpn., 24 (5): 73-82 (1993)Cascade Realization of 3-Input 3-Output Conservative Logic Circuits., and . IEEE Trans. Computers, 27 (3): 214-221 (1978)Design of High-Level Test Language for Digital LSI., , and . ITC, page 508-513. IEEE Computer Society, (1983)Resynthesis for sequential circuits designed with a specified initial state., , and . VTS, page 152-157. IEEE Computer Society, (1995)On Test Generation with A Limited Number of Tests., , and . Great Lakes Symposium on VLSI, page 12-15. IEEE Computer Society, (1999)Partially Parallel Scan Chain for Test Length Reduction by Using Retiming Technique., , and . Asian Test Symposium, page 94-99. IEEE Computer Society, (1996)Procedure to Overcome the Byzantine General's Problem for Bridging Faults in CMOS Circuits., , and . Asian Test Symposium, page 121-126. IEEE Computer Society, (1999)An Algorithmic Test Generation Method for Crosstalk Faults in Synchronous Sequential Circuits., , and . Asian Test Symposium, page 22-. IEEE Computer Society, (1997)