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FPGA Architecture Design and Toolset for Logic Implementation.

, , , , , , and . PATMOS, volume 2799 of Lecture Notes in Computer Science, page 607-616. Springer, (2003)

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An Integrated Framework for Architecture Level Exploration of Reconfigurable Platform., , , , and . FPL, page 658-661. IEEE, (2005)A novel division algorithm for parallel and sequential processing., , , , and . ICECS, page 553-556. IEEE, (2002)FPGA Architecture Design and Toolset for Logic Implementation., , , , , , and . PATMOS, volume 2799 of Lecture Notes in Computer Science, page 607-616. Springer, (2003)A CAD tool for architecture level exploration and automatic generation of RNS converters., , , and . ISCAS (4), page 730-733. IEEE, (2001)The design of low power multiple-valued logic encoder and decoder circuits., , , and . ICECS, page 1623-1626. IEEE, (1999)An Integrated FPGA Design Framework: Custom Designed FPGA Platform and Application Mapping Toolset Development., , , , , , , , , and . IPDPS, IEEE Computer Society, (2004)A complete platform and toolset for system implementation on fine-grain reconfigurable hardware., , , , , , , , , and . Microprocess. Microsystems, 29 (6): 247-259 (2005)Designing RNS and QRNS full adder based converters., , and . ISCAS, page 20-23. IEEE, (2000)