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Glitch-free discretely programmable clock generation on chip.

, , и . ISCAS (2), стр. 1839-1842. IEEE, (2005)

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Francesco Bettella

Protein secondary structure prediction using optimized scoring functions: a comparative statistical method. FU Berlin, (2009)

Francesco Solimena

Francesco Pinosa

Francesco Knechtli

Francesco Virili

 

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MDSP: A High-Performance Low-Power DSP Architecture., , и . PATMOS, том 2451 из Lecture Notes in Computer Science, стр. 35-44. Springer, (2002)Heterogeneous Clustered Processors: Organisation and Design.. Euro-Par, том 1685 из Lecture Notes in Computer Science, стр. 1296-1300. Springer, (1999)Limits to performance spread tuning using adaptive voltage and body biasing., , и . ISCAS (1), стр. 5-8. IEEE, (2005)How to determine the necessity for emerging solutions., , , , , и . DAC, стр. 274-275. ACM, (2005)Analysis of High-Speed Logic Families., и . PATMOS, том 2799 из Lecture Notes in Computer Science, стр. 2-10. Springer, (2003)Glitch-free discretely programmable clock generation on chip., , и . ISCAS (2), стр. 1839-1842. IEEE, (2005)The Holy Grail of Holistic Low-Power Design.. PATMOS, том 4148 из Lecture Notes in Computer Science, стр. 671. Springer, (2006)Technology exploration for adaptive power and frequency scaling in 90nm CMOS., , и . ISLPED, стр. 14-19. ACM, (2004)Asynchronous First-in First-out Queues., и . PATMOS, том 1918 из Lecture Notes in Computer Science, стр. 178-186. Springer, (2000)A 260ps Quasi-static ALU in 90nm CMOS., и . PATMOS, том 3254 из Lecture Notes in Computer Science, стр. 372-380. Springer, (2004)