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Optimization of the Body Bias Voltage Set (BBVS) for Flex Power FPGA.

, , , , , , and . IEICE Trans. Inf. Syst., 90-D (12): 1947-1955 (2007)

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Preliminary Evaluation of Flex Power FPGA: A Power Reconfigurable Architecture with Fine Granularity., , , , , , and . IEICE Trans. Inf. Syst., 87-D (8): 2004-2010 (2004)Preliminary performance analysis of flex power FPGA, a power reconfigurable device with fine granularity., , , , , , and . FPGA, page 257. ACM, (2004)Realization of 0.7-V analog circuits by adaptive-Vt operation of FinFET., , , , , , , , , and 1 other author(s). CICC, page 1-4. IEEE, (2010)High-Frequency Precise Characterization of Intrinsic FinFET Channel., , , , , , , , , and 3 other author(s). IEICE Trans. Electron., 95-C (4): 752-760 (2012)Optimization of the Body Bias Voltage Set (BBVS) for Flex Power FPGA., , , , , , and . IEICE Trans. Inf. Syst., 90-D (12): 1947-1955 (2007)A 0.7-V Opamp in Scaled Low-Standby-Power FinFET Technology., , , , , , , , , and 2 other author(s). IEICE Trans. Electron., 95-C (4): 686-695 (2012)Optimal set of body bias voltages for an FPGA with field-programmable Vth components., , , , , , and . FPT, page 329-332. IEEE, (2006)A Power Configurable Block Array Connected in Series as First Prototype Flex Power FPGA Chip., , , , , , and . FPT, page 285-288. IEEE, (2007)Suppression of Intrinsic Delay Variation in FPGAs using Multiple Configurations., , , , , , and . ACM Trans. Reconfigurable Technol. Syst., 1 (1): 3:1-3:31 (2008)0.5V FinFET SRAM with dynamic threshold control of pass gates for salvaging malfunctioned bits., , , , , , , , , and 2 other author(s). ESSCIRC, page 474-477. IEEE, (2010)