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Power and performance trade-offs for Space Time Adaptive Processing.

, , , , , and . ASAP, page 41-48. IEEE Computer Society, (2015)

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Evolutionary algorithms for the mapping of pipelined applications onto heterogeneous embedded systems., , , , , , and . GECCO, page 1435-1442. ACM, (2009)Multiprocessor systems-on-chip synthesis using multi-objective evolutionary computation., , , , and . GECCO, page 1267-1274. ACM, (2010)Scaling and Quality of Modularity Optimization Methods for Graph Clustering., , , and . HPEC, page 1-6. IEEE, (2019)Performance modeling of parallel applications on MPSoCs., , , and . SoC, page 64-67. IEEE, (2009)From High-Level Frameworks to custom Silicon with SODA., , , , , , , , , and 3 other author(s). HCS, page 1-13. IEEE, (2022)MLIR Loop Optimizations for High-Level Synthesis: A Case Study., , , , and . PACT, page 544-545. ACM, (2022)AXI4MLIR: User-Driven Automatic Host Code Generation for Custom AXI-Based Accelerators., , , , , , , , and . CGO, page 143-157. IEEE, (2024)Emulating Transactional Memory on FPGA Multiprocessors., , , , and . ARCS, volume 6566 of Lecture Notes in Computer Science, page 74-85. Springer, (2011)High-level synthesis of memory bound and irregular parallel applications with Bambu., , and . Hot Chips Symposium, page 1. IEEE, (2014)A dynamically scheduled architecture for the synthesis of graph methods., , , , and . Hot Chips Symposium, page 1-7. IEEE, (2016)