From post

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed.

 

Другие публикации лиц с тем же именем

A middle-grain circuit partitioning strategy for 3-D integrated floating-point multipliers., , , , и . 3DIC, стр. 1-6. IEEE, (2011)Vertically integrated processor and memory module design for vector supercomputers., , , и . 3DIC, стр. 1-6. IEEE, (2013)A Capacity-Aware Thread Scheduling Method Combined with Cache Partitioning to Reduce Inter-Thread Cache Conflicts., , , и . IEICE Trans. Inf. Syst., 96-D (9): 2047-2054 (2013)OpenCL-like offloading with metaprogramming for SX-Aurora TSUBASA., , , и . Parallel Comput., (2021)Improving Quantum Annealing Performance on Embedded Problems., , , и . Supercomput. Front. Innov., 7 (4): 32-48 (2020)An Adjacent-Line-Merging Writeback Scheme for STT-RAM-Based Last-Level Caches., , , , и . IEEE Trans. Multi Scale Comput. Syst., 4 (4): 593-604 (2018)An Adjacent-Line-Merging Writeback Scheme for STT-RAM last-level caches., , , и . COOL Chips, стр. 1-2. IEEE Computer Society, (2017)An energy-efficient dynamic memory address mapping mechanism., , , , , и . COOL Chips, стр. 1-3. IEEE Computer Society, (2015)Cache partitioning strategies for 3-D stacked vector processors., , , и . 3DIC, стр. 1-6. IEEE, (2010)Automatically Avoiding Memory Access Conflicts on SX-Aurora TSUBASA., , , , и . IPDPS Workshops, стр. 822-829. IEEE, (2020)