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Disambiguation of "Sato, Masayuki"

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An Adjacent-Line-Merging Writeback Scheme for STT-RAM-Based Last-Level Caches.

, , , , and . IEEE Trans. Multi Scale Comput. Syst., 4 (4): 593-604 (2018)

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Masayuki Hirosue

Makoto Sato

Masayuki Maenishi

Masayuki Yamamoto

Nobuko Sato

 

Other publications of authors with the same name

Nozzleless EHD Spraying for Fine Droplet Production in Liquid-In-Liquid System., , , , , and . IAS, page 1-5. IEEE, (2009)Study of Eradicating Invasive Organisms from Ballast Water with Pulsed Discharge in Liquid., , , and . IAS, page 1-3. IEEE, (2009)Automatic composition system based on genetic algorithm and N-gram model., , and . SMC, page 202-207. IEEE, (2008)A Physical Design Method for a New Memory-Based Reconfigurable Architecture without Switch Blocks., , , , , and . IEICE Trans. Inf. Syst., 95-D (2): 324-334 (2012)A Layer-Adaptable Cache Hierarchy by a Multiple-layer Bypass Mechanism., , , and . HEART, page 12:1-12:6. ACM, (2019)Hardware-in-the-loop evaluation of an LPV sliding mode fixed control allocation scheme on the MuPAL-α research aircraft., , , and . CCTA, page 590-595. IEEE, (2017)Optimizing Memory Layout of Hyperplane Ordering for Vector Supercomputer SX-Aurora TSUBASA., , , , , and . MCHPC@SC, page 25-32. IEEE, (2019)Performance evaluation of a vector supercomputer SX-aurora TSUBASA., , , , , , , , and . SC, page 54:1-54:12. IEEE / ACM, (2018)A Skewed Multi-banked Cache for Many-core Vector Processors., , , and . Supercomput. Front. Innov., 6 (3): 86-101 (2019)A Metadata Prefetching Mechanism for Hybrid Memory Architectures., , , , and . IEICE Trans. Electron., 105-C (6): 232-243 (2022)