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Mixed-Signal Charge-Domain Acceleration of Deep Neural Networks through Interleaved Bit-Partitioned Arithmetic.

, , , , , , , и . PACT, стр. 399-411. ACM, (2020)

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On-Chip Interconnection Networks of the TRIPS Chip., , , , , , и . IEEE Micro, 27 (5): 41-50 (2007)A Neuroevolution Method for Dynamic Resource Allocation on a Chip Multiprocessor, , и . Proceedings of the INNS-IEEE International Joint Conference on Neural Networks, стр. 2355--2361. Piscataway, NJ, IEEE, (2001)Microprocessor pipeline energy analysis., , , , и . ISLPED, стр. 282-287. ACM, (2003)Memory Systems., , и . The Computer Science and Engineering Handbook, CRC Press, (1997)Multicore Model from Abstract Single Core Inputs., , , , и . IEEE Comput. Archit. Lett., 12 (2): 59-62 (2013)Register Bank Assignment for Spatially Partitioned Processors., , , и . LCPC, том 5335 из Lecture Notes in Computer Science, стр. 64-79. Springer, (2008)Billion-Transistor Architectures - Guest Editors' Introduction., и . Computer, 30 (9): 46-49 (1997)Scalable Hardware Memory Disambiguation for High ILP Processors., , , , и . MICRO, стр. 399-410. IEEE Computer Society, (2003)Dataflow Predication., , , , , , и . MICRO, стр. 89-102. IEEE Computer Society, (2006)Distributed Microarchitectural Protocols in the TRIPS Prototype Processor., , , , , , , , , и 7 other автор(ы). MICRO, стр. 480-491. IEEE Computer Society, (2006)