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3D Stackable Vertical Ferroelectric Tunneling Junction (V-FTJ) with on/off Ratio 1500x, Applicable Cell Current, Self-Rectifying Ratio 1000x, Robust Endurance of 10⁹ Cycles, Multilevel and Demonstrated Macro Operation Toward High-Density BEOL NVMs.

, , , , , , , , and . VLSI Technology and Circuits, page 1-2. IEEE, (2023)

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Steep Switching of In0.18Al0.82N/AlN/GaN MIS-HEMT (Metal Insulator Semiconductor High Electron Mobility Transistors) on Si for Sensor Applications., , , , , and . Sensors, 18 (9): 2795 (2018)Interfacial-Layer Design for Hf1-xZrxO2-Based FTJ Devices: From Atom to Array., , , , , , , , , and 6 other author(s). VLSI Technology and Circuits, page 361-362. IEEE, (2022)Cryogenic Endurance of Anti-ferroelectric and Ferroelectric Hf1-xZrXO2 for Quantum Computing Applications., , , , , , , , and . IRPS, page 1-4. IEEE, (2023)Double Layers Omega FETs with Ferroelectric HfZrO2 for One-Transistor Memory., , , , , , , , , and 12 other author(s). IRPS, page 1-4. IEEE, (2020)Endurance > 1011 Cycling of 3D GAA Nanosheet Ferroelectric FET with Stacked HfZrO2 to Homogenize Corner Field Toward Mitigate Dead Zone for High-Density eNVM., , , , , , , , , and 4 other author(s). VLSI Technology and Circuits, page 1-2. IEEE, (2022)3D Stackable Vertical Ferroelectric Tunneling Junction (V-FTJ) with on/off Ratio 1500x, Applicable Cell Current, Self-Rectifying Ratio 1000x, Robust Endurance of 10⁹ Cycles, Multilevel and Demonstrated Macro Operation Toward High-Density BEOL NVMs., , , , , , , , and . VLSI Technology and Circuits, page 1-2. IEEE, (2023)Correlation between Access Polarization and High Endurance (~ 1012 cycling) of Ferroelectric and Anti-Ferroelectric HfZrO2., , , , , , , , , and 5 other author(s). IRPS, page 9-1. IEEE, (2022)FeRAM Recovery up to 200 Periods with Accumulated Endurance 1012 Cycles and an Applicable Array Circuit toward Unlimited eNVM Operations., , , , , , , , , and . VLSI Technology and Circuits, page 1-2. IEEE, (2023)Impact of nanoscale polarization relaxation on endurance reliability of one-transistor hybrid memory using combined storage mechanisms., , , , and . IRPS, page 3. IEEE, (2015)First Stacked Nanosheet FeFET Featuring Memory Window of 1.8V at Record Low Write Voltage of 2V and Endurance >1E11 Cycles., , , , , , , , , and 5 other author(s). VLSI Technology and Circuits, page 1-2. IEEE, (2023)