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A 2 Gb/s balanced AES crypto-chip implementation., , , , , , and . ACM Great Lakes Symposium on VLSI, page 39-44. ACM, (2004)Exploiting dynamic timing margins in microprocessors for frequency-over-scaling with instruction-based clock adjustment., , , , and . DATE, page 381-386. ACM, (2015)Adding Indoor Capacity Without Fiber Backhaul: A mmWave Bridge Prototype., , and . CoRR, (2021)Silicon implementation of an MMSE-based soft demapper for MIMO-BICM., , , , , and . ISCAS, IEEE, (2006)LoRa Digital Receiver Analysis and Implementation., , , and . CoRR, (2018)Configurable high-throughput decoder architecture for quasi-cyclic LDPC codes., , , and . ACSCC, page 1137-1142. IEEE, (2008)Increasing LoRa Sensitivity and Reliability with an IoT Cloud RAN., and . ACSSC, page 197-201. IEEE, (2023)Automated Integration of Dual-Edge Clocking for Low-Power Operation in Nanometer Nodes., , , and . ACM Trans. Design Autom. Electr. Syst., 22 (4): 62:1-62:20 (2017)Density Evolution for Min-Sum Decoding of LDPC Codes Under Unreliable Message Storage., and . IEEE Commun. Lett., 18 (5): 849-852 (2014)List Ordered Statistics Decoders for Polar Codes., , , , , and . IEEECONF, page 628-633. IEEE, (2022)