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Disambiguation of "Ko, Hyungjong"

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20.3 A 4.0×3.7×1.0mm3-MEMS CMOS Integrated E-Nose with Embedded 4×Gas Sensors, a Temperature Sensor and a Relative Humidity Sensor.

, , , , , , , , , , , , , , and . ISSCC, page 316-318. IEEE, (2020)

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Insok Ko

Yousun Ko

Yousik Ko

Annette Ko

Ko Endo

 

Other publications of authors with the same name

A 16-Gb T-Coil-Based GDDR6 DRAM With Merged-MUX TX, Optimized WCK Operation, and Alternative-Data-Bus Achieving 27-Gb/s/Pin in NRZ., , , , , , , , , and 24 other author(s). IEEE J. Solid State Circuits, 58 (1): 279-290 (2023)20.3 A 4.0×3.7×1.0mm3-MEMS CMOS Integrated E-Nose with Embedded 4×Gas Sensors, a Temperature Sensor and a Relative Humidity Sensor., , , , , , , , , and 5 other author(s). ISSCC, page 316-318. IEEE, (2020)A 3.2-12.8Gb/s Duty-Cycle Compensating Quadrature Error Corrector for DRAM Interfaces, With Fast Locking and Low Power Characteristics., , , , , , , , , and 4 other author(s). ESSCIRC, page 463-466. IEEE, (2021)A 16Gb 27Gb/s/pin T-coil based GDDR6 DRAM with Merged-MUX TX, Optimized WCK Operation, and Alternative-Data-Bus., , , , , , , , , and 24 other author(s). ISSCC, page 446-448. IEEE, (2022)A 24Gb/s/pin PAM-4 Built Out Tester chip enabling PAM-4 chips test with NRZ interface ATE., , , , , , , , , and . A-SSCC, page 1-3. IEEE, (2021)A 40-Gb/s/pin Low-Voltage POD Single-Ended PAM-4 Transceiver with Timing Calibrated Reset-less Slicer and Bidirectional T-Coil for GDDR7 Application., , , , , , , , , and 13 other author(s). VLSI Technology and Circuits, page 148-149. IEEE, (2022)A 4ns Settling Time FVF-Based Fast LDO Using Bandwidth Extension Techniques for HBM3., , , , , , , , , and 4 other author(s). A-SSCC, page 1-3. IEEE, (2023)An 8nm All-Digital 7.3Gb/s/pin LPDDR5 PHY with an Approximate Delay Compensation Scheme., , , , , , , , , and 8 other author(s). VLSI Circuits, page 96-. IEEE, (2019)A 12-Gb/s Baud-Rate Clock and Data Recovery With 75% Phase-Detection Probability by Precoding and Integration-Hold-Reset Frontend., , , , , , , , , and 1 other author(s). IEEE Trans. Circuits Syst. II Express Briefs, 70 (2): 411-415 (February 2023)A 60-Gb/s/pin single-ended PAM-4 transmitter with timing skew training and low power data encoding in mimicked 10nm class DRAM process., , , , , , , , , and 18 other author(s). CICC, page 1-2. IEEE, (2022)