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Introduction to the Minitrack on Digital Twins: Platforms, Methods, Applications, and Impact.

, , and . HICSS, page 6746-6747. ScholarSpace, (2023)

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A model-based design space exploration for embedded image processing in industrial applications., , , , and . INDIN, page 434-439. IEEE, (2014)Implementation of the AES Algorithm for a Reconfigurable, Bit Serial, Fully Pipelined Architecture., and . ARC, volume 5453 of Lecture Notes in Computer Science, page 330-335. Springer, (2009)Model-Based Design Methodology for Early Evaluation of Real-time and Embedded Constraints., , , , and . INDIN, page 875-881. IEEE, (2018)Control Development for Mechatronic Systems with a Fully Reconfigurable Pipeline Architecture., , , , and . SBCCI, page 231-236. IEEE Computer Society, (2003)Communication Layer Architecture for a Production Line Digital Twin Using Hierarchical Colored Petri Nets., , and . IESS, volume 669 of IFIP Advances in Information and Communication Technology, page 41-50. Springer, (2022)Combining an Iterative State-Based Timing Analysis with a Refinement Checking Technique., , and . IESS, volume 523 of IFIP Advances in Information and Communication Technology, page 88-99. Springer, (2015)A Proposal to Trace and Maintain Requirements Constraints of Real-time Embedded Systems., , , , and . IESS, volume 576 of IFIP Advances in Information and Communication Technology, page 15-26. Springer, (2019)Spezielle Aspekte der Verlustleistungsgetriebenen High-Level Synthese., , and . GI Jahrestagung (1), volume P-67 of LNI, page 455. GI, (2005)Towards Formalized Model-Based Requirements for a Seamless Design Approach in Safety-Critical Systems Development., , and . ISORC Workshops, page 111-115. IEEE Computer Society, (2015)A new Design Partitioning Approach for Low Power High-Level Synthesis., and . DELTA, page 143-148. IEEE Computer Society, (2006)