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Disambiguation of "Hida, Hikaru"

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Low-power-consumption direct-conversion CMOS transceiver for multi-standard 5-GHz wireless LAN systems with channel bandwidths of 5-20 MHz.

, , , , , , , , , , , , and . IEEE J. Solid State Circuits, 41 (2): 375-383 (2006)

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Y. Hidalgo-Delgado

Arnan Hidalgo

Emilio Hidalgo-Serna

Sylvia Santosa Hidajat

Nico Santosa Hidajat

 

Other publications of authors with the same name

Low-Power Widely Tunable Gm-C Filter Employing an Adaptive DC-blocking, Triode-Biased MOSFET Transconductor., , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 61-I (1): 37-47 (2014)Low supply voltage operation of over-40-Gb/s digital ICs based on parallel-current-switching latch circuitry., , , , and . IEEE J. Solid State Circuits, 40 (10): 2111-2117 (2005)An efficient algorithm for simulating error vector magnitude in nonlinear OFDM amplifiers., , and . CICC, page 129-132. IEEE, (2004)Application of Microwave and Millimeter-Wave Circuit Technologies to InGaP-HBT ICs for 40-Gbps Optical Transmission Systems., , , , , , , , , and . IEICE Trans. Electron., 90-C (9): 1685-1694 (2007)A Low-Power Dual-Band Triple-Mode WLAN CMOS Transceiver., , , , , , , , , and 2 other author(s). IEEE J. Solid State Circuits, 41 (11): 2481-2490 (2006)Low-power-consumption direct-conversion CMOS transceiver for multi-standard 5-GHz wireless LAN systems with channel bandwidths of 5-20 MHz., , , , , , , , , and 3 other author(s). IEEE J. Solid State Circuits, 41 (2): 375-383 (2006)120-Gb/s multiplexing and 110-Gb/s demultiplexing ICs., , , , , , , and . IEEE J. Solid State Circuits, 39 (12): 2397-2402 (2004)Low-power widely tunable Gm-C filter with an adaptive DC-blocking, triode-biased MOSFET transconductor., , , and . ESSCIRC, page 99-102. IEEE, (2004)OFDM Error Vector Magnitude Distortion Analysis., , and . IEICE Trans. Electron., 89-C (12): 1836-1842 (2006)