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Disambiguation of "Burg, Andreas"

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MIMO transmission with residual transmit-RF impairments.

, , and . WSA, page 189-196. IEEE, (2010)

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Andreas Burg

Andreas Marzell Burg

Richard Burg

Arnold Burg

Helmut Burg

 

Other publications of authors with the same name

Silicon implementation of an MMSE-based soft demapper for MIMO-BICM., , , , , and . ISCAS, IEEE, (2006)LoRa Digital Receiver Analysis and Implementation., , , and . CoRR, (2018)Adding Indoor Capacity Without Fiber Backhaul: A mmWave Bridge Prototype., , and . CoRR, (2021)Configurable high-throughput decoder architecture for quasi-cyclic LDPC codes., , , and . ACSCC, page 1137-1142. IEEE, (2008)A 2 Gb/s balanced AES crypto-chip implementation., , , , , , and . ACM Great Lakes Symposium on VLSI, page 39-44. ACM, (2004)Exploiting dynamic timing margins in microprocessors for frequency-over-scaling with instruction-based clock adjustment., , , , and . DATE, page 381-386. ACM, (2015)Increasing LoRa Sensitivity and Reliability with an IoT Cloud RAN., and . ACSSC, page 197-201. IEEE, (2023)VLSI Implementation of Hard- and Soft-Output Sphere Decoding for Wide-Band MIMO Systems., , and . VLSI-SoC (Selected Papers), volume 373 of IFIP Advances in Information and Communication Technology, page 128-154. Springer, (2010)Low-complexity frequency synchronization for GSM systems: Algorithms and implementation., , , , and . ICUMT, page 168-173. IEEE, (2012)A 0.5 V 2.5 μW/MHz Microcontroller with Analog-Assisted Adaptive Body Bias PVT Compensation with 3.13nW/kB SRAM Retention in 55nm Deeply-Depleted Channel CMOS., , , , , , , , and . CICC, page 1-4. IEEE, (2019)