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Disambiguation of "Ndai, Patrick"

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Design Paradigm for Robust Spin-Torque Transfer Magnetic RAM (STT MRAM) From Circuit/Architecture Perspective.

, , , , and . IEEE Trans. Very Large Scale Integr. Syst., 18 (12): 1710-1723 (2010)

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Patrick Pfeffer

Optimiertes Design kombinatorischer Verbindungsbibliotheken durch genetische Algorithmen und deren Bewertung anhand wissensbasierter Protein-Ligand-Bindungsprofile. Uni Marburg, (2009)

Patrick Hansen

Entwicklung eines energetischen Sanierungsmodells für den europäischen Wohngebäudesektor unter dem Aspekt der Erstellung von Szenarien für Energie- und Co_1tn2-Einsparpotenziale bis 2030. Uni Siegen, (2009)

Ekkehard Patrick

Patrick Fleischmann

Patrick Horster

 

Other publications of authors with the same name

Design Paradigm for Robust Spin-Torque Transfer Magnetic RAM (STT MRAM) From Circuit/Architecture Perspective., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 18 (12): 1710-1723 (2010)O2C: occasional two-cycle operations for dynamic thermal management in high performance in-order microprocessors., , , and . ISLPED, page 189-192. ACM, (2008)A Read-Disturb-Free, Differential Sensing 1R/1W Port, 8T Bitcell Array., , , and . IEEE Trans. Very Large Scale Integr. Syst., 19 (9): 1727-1730 (2011)Fine-Grained Redundancy in Adders., , , and . ISQED, page 317-321. IEEE Computer Society, (2007)A Soft Error Monitor Using Switching Current Detection., , , and . ICCD, page 185-192. IEEE Computer Society, (2005)A Scalable Circuit-Architecture Co-Design to Improve Memory Yield for High-Performance Processors., , and . IEEE Trans. Very Large Scale Integr. Syst., 18 (8): 1209-1219 (2010)A Novel Low Overhead Fault Tolerant Kogge-Stone Adder Using Adaptive Clocking., , and . DATE, page 366-371. ACM, (2008)Tolerance to Small Delay Defects by Adaptive Clock Stretching., , , and . IOLTS, page 244-252. IEEE Computer Society, (2007)REad/access-preferred (REAP) SRAM - architecture-aware bit cell design for improved yield and lower VMIN., , , and . CICC, page 503-506. IEEE, (2009)Within-Die Variation-Aware Scheduling in Superscalar Processors for Improved Throughput., , , and . IEEE Trans. Computers, 57 (7): 940-951 (2008)