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Blocker and jitter tolerant wideband ΣΔ modulators., , and . MWSCAS, page 390-393. IEEE, (2012)Design Techniques to Improve Blocker Tolerance of Continuous-Time ΔΣ ADCs., , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 23 (1): 54-67 (2015)27.6 A 4GS/s 13b pipelined ADC with capacitor and amplifier sharing in 16nm CMOS., , , , , , , , , and 13 other author(s). ISSCC, page 466-467. IEEE, (2016)A current-mode flash ADC for low-power continuous-time sigma delta modulators., , , , and . ISCAS, page 141-144. IEEE, (2013)26.6 A 5GS/S 150mW 10b SHA-less pipelined/SAR hybrid ADC in 28nm CMOS., , , , , , , , , and 13 other author(s). ISSCC, page 1-3. IEEE, (2015)Efficient Broadband Current-Mode Adder- Quantizer Design for Continuous-Time Sigma-Delta Modulators., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 23 (9): 1920-1930 (2015)Blocker tolerant wideband continuous time sigma-delta modulator for wireless applications., , , and . MWSCAS, page 765-768. IEEE, (2014)Fully balanced low-noise transconductance amplifiers with P1dB > 0dBm in 45nm CMOS., , and . ESSCIRC, page 231-234. IEEE, (2011)