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Hardware/Software Co-Exploration of Neural Architectures., , , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 39 (12): 4805-4815 (2020)Contour: A Process Variation Aware Wear-Leveling Mechanism for Inodes of Persistent Memory File Systems., , , , , and . IEEE Trans. Computers, 70 (7): 1034-1045 (2021)Device-Circuit-Architecture Co-Exploration for Computing-in-Memory Neural Accelerators., , , , , , and . IEEE Trans. Computers, 70 (4): 595-605 (2021)VACSEN: A Visualization Approach for Noise Awareness in Quantum Computing., , , , and . CoRR, (2022)Towards the design of efficient hash-based indexing scheme for growing databases on non-volatile memory., , , , , and . Future Gener. Comput. Syst., (2020)One Proxy Device Is Enough for Hardware-Aware Neural Architecture Search., , , , and . SIGMETRICS (Abstracts), page 55-56. ACM, (2022)Toward Consistent High-Fidelity Quantum Learning on Unstable Devices via Efficient In-Situ Calibration., , , , , and . QCE, page 848-858. IEEE, (2023)All-in-One: A Highly Representative DNN Pruning Framework for Edge Devices with Dynamic Power Management., , , , , , , , and . ICCAD, page 133:1-133:9. ACM, (2022)On the Design of Quantum Graph Convolutional Neural Network in the NISQ-Era and Beyond., , , , , , , , and . ICCD, page 290-297. IEEE, (2022)Muffin: A Framework Toward Multi-Dimension AI Fairness by Uniting Off-the-Shelf Models., , , , , and . DAC, page 1-6. IEEE, (2023)