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Layout Synthesis for Topological Quantum Circuits With 1-D and 2-D Architectures.

, , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 37 (8): 1574-1587 (2018)

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Global Routing., and . Encyclopedia of Algorithms, (2016)A high-performance triple patterning layout decomposer with balanced density., , , , , and . ICCAD, page 163-169. IEEE, (2013)Total power optimization combining placement, sizing and multi-Vt through slack distribution management., , and . ASP-DAC, page 352-357. IEEE, (2008)BOB-router: A new buffering-aware global router with over-the-block routing resources optimization., , and . ASP-DAC, page 513-518. IEEE, (2014)Self-aligned double patterning layout decomposition with complementary e-beam lithography., , and . ASP-DAC, page 143-148. IEEE, (2014)Layout-dependent aging mitigation for critical path timing., , , , , , , and . ASP-DAC, page 153-158. IEEE, (2018)Machine learning and pattern matching in physical design., , , and . ASP-DAC, page 286-293. IEEE, (2015)Light in AI: Toward Efficient Neurocomputing With Optical Neural Networks - A Tutorial., , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 69 (6): 2581-2585 (2022)PiPSim: A Behavior-Level Modeling Tool for CNN Processing-in-Pixel Accelerators., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 43 (1): 141-150 (January 2024)Impact of Mechanical Stress on the Full Chip Timing for Through-Silicon-Via-based 3-D ICs., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 32 (6): 905-917 (2013)