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Impact of technology scaling on substrate noise generation mechanisms mixed signal ICs.

, , , , , and . CICC, page 501-504. IEEE, (2004)

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Clock tree optimization in synchronous CMOS digital circuits for substrate noise reduction using folding of supply current transients., , , , , , and . DAC, page 399-404. ACM, (2002)Digital ground bounce reduction by supply current shaping and clock frequency Modulation., , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 24 (1): 65-76 (2005)High-Level Power Minimization of Analog Sensor Interface Architectures., , and . Integr. Comput. Aided Eng., 5 (4): 303-314 (1998)Compensation of transmitter IQ imbalance for OFDM systems., , , , , and . ICASSP (2), page 325-328. IEEE, (2004)OFDM versus Single Carrier with Cyclic Prefix: a system-based comparison., , , , , and . VTC Fall, page 1115-1119. IEEE, (2001)A Single-Package Solution for Wireless Transceivers., , , , , and . DATE, page 425-. IEEE Computer Society / ACM, (1999)Digital Ground Bounce Reduction by Phase Modulation of the Clock., , , , , and . DATE, page 88-93. IEEE Computer Society, (2004)Modeling of Substrate Noise Generation, Isolation, and Impact for an LC-VCO and a Digital Modem on a Lightly-Doped Substrate., , , , , , and . IEEE J. Solid State Circuits, 41 (9): 2040-2051 (2006)Scalable Gate-Level Models for Power and Timing Analysis., , , , , and . ISCAS, page 2938-2941. IEEE, (2007)A 328 μW 5 GHz voltage-controlled oscillator in 90 nm CMOS with high-quality thin-film post-processed inductor., , , , , , , , , and 3 other author(s). CICC, page 701-704. IEEE, (2004)