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4.8 An Area and Energy Efficient 0.12nJ/Pixel 8K 30fps AV1 Video Decoder in 5nm CMOS Process.

, , , , , , , , , , , , , and . ISSCC, page 68-70. IEEE, (2021)

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SYMTUNER: Maximizing the Power of Symbolic Execution by Adaptively Tuning External Parameters., , , and . ICSE, page 2068-2079. ACM, (2022)Critical-path-aware high-level synthesis with distributed controller for fast timing closure., and . ACM Trans. Design Autom. Electr. Syst., 19 (2): 16:1-16:29 (2014)AIRS-assisted Vehicular Networks with Rate-Splitting SWIPT Receivers: Joint Trajectory and Communication Design., , and . CoRR, (2024)Effective white-box testing of deep neural networks with adaptive neuron-selection strategy., , , and . ISSTA, page 165-176. ACM, (2020)4.8 An Area and Energy Efficient 0.12nJ/Pixel 8K 30fps AV1 Video Decoder in 5nm CMOS Process., , , , , , , , , and 4 other author(s). ISSCC, page 68-70. IEEE, (2021)Routing-Aware Application Mapping Considering Steiner Points for Coarse-Grained Reconfigurable Architecture., , , and . ARC, volume 5992 of Lecture Notes in Computer Science, page 231-243. Springer, (2010)Communication architecture design for reconfigurable multimedia SoC platform., , , , , and . Des. Autom. Embed. Syst., 14 (1): 1-20 (2010)Automatic Bus Matrix Synthesis based on Hardware Interface Selection for Fast Communication Design Space Exploration., , , and . ICSAMOS, page 50-57. IEEE, (2007)High-level synthesis with distributed controller for fast timing closure., and . ICCAD, page 193-199. IEEE Computer Society, (2011)