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Large-Memory Nodes for Energy Efficient High-Performance Computing., , , , , , , and . MEMSYS, page 3-9. ACM, (2016)Multilevel simulation-based co-design of next generation HPC microprocessors., , , , , , , , , and 10 other author(s). PMBS, page 18-29. IEEE, (2021)Mainstream vs. Emerging HPC: Metrics, Trade-Offs and Lessons Learned., , , , , , , , , and 1 other author(s). SBAC-PAD, page 250-257. IEEE, (2018)Main Memory in HPC: Do We Need More or Could We Live with Less?, , , , , , , , and . ACM Trans. Archit. Code Optim., 14 (1): 3:1-3:26 (2017)Performance Impact of a Slower Main Memory: A case study of STT-MRAM in HPC., , , , , , and . MEMSYS, page 40-49. ACM, (2016)Main memory latency simulation: the missing link., , , , , and . MEMSYS, page 107-116. ACM, (2018)Another Trip to the Wall: How Much Will Stacked DRAM Benefit HPC?, , , , , , and . MEMSYS, page 31-36. ACM, (2015)Memory bandwidth and latency in HPC: system requirements and performance impact.. Polytechnic University of Catalonia, Spain, (2019)Industrial Single Board Computer based on OMAP5 processor., , , and . MECO, page 84-87. IEEE, (2013)HPC Benchmarking: Scaling Right and Looking Beyond the Average., , , , and . Euro-Par, volume 11014 of Lecture Notes in Computer Science, page 135-146. Springer, (2018)