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Disambiguation of "Hsieh, Chih-Cheng"

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Two-Way Transpose Multibit 6T SRAM Computing-in-Memory Macro for Inference-Training AI Edge Chips.

, , , , , , , , , , , , , , , , , , , , , , , , and . IEEE J. Solid State Circuits, 57 (2): 609-624 (2022)

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Chih-Peng Hsieh

Chih-sheng Hsieh

Chih-Jen Hsieh

Chih-Cheng Jeng

Chih-Hong Cheng

 

Other publications of authors with the same name

Time-delay integration readout with adjacent pixel signal transfer for CMOS image sensor., , , , , and . VLSI-DAT, page 1-4. IEEE, (2012)A 12 bit 150 MS/s 1.5 mW SAR ADC with adaptive radix DAC in 40 nm CMOS., and . A-SSCC, page 157-160. IEEE, (2016)A 0.3 V 10-bit 1.17 f SAR ADC With Merge and Split Switching in 90 nm CMOS., and . IEEE Trans. Circuits Syst. I Regul. Pap., 62-I (1): 70-79 (2015)A 12-bit 150-MS/s Sub-Radix-3 SAR ADC With Switching Miller Capacitance Reduction., and . IEEE J. Solid State Circuits, 53 (6): 1755-1764 (2018)A 2.02-5.16 fJ/Conversion Step 10 Bit Hybrid Coarse-Fine SAR ADC With Time-Domain Quantizer in 90 nm CMOS., , and . IEEE J. Solid State Circuits, 51 (2): 357-364 (2016)A CMOS Time-of-Flight Depth Image Sensor With In-Pixel Background Light Cancellation and Phase Shifting Readout Technique., , , and . IEEE J. Solid State Circuits, 53 (10): 2898-2905 (2018)A 0.5-V 12-bit SAR ADC Using Adaptive Time-Domain Comparator With Noise Optimization., , and . IEEE J. Solid State Circuits, 53 (10): 2763-2771 (2018)A signal acquisition and processing chip with built-in cluster for chemiresistive gas sensor array., , , , , , , , and . NEWCAS, page 428-431. IEEE, (2014)A Floating-Point 6T SRAM In-Memory-Compute Macro Using Hybrid-Domain Structure for Advanced AI Edge Chips., , , , , , , , , and 7 other author(s). IEEE J. Solid State Circuits, 59 (1): 196-207 (January 2024)An 8b-Precision 8-Mb STT-MRAM Near-Memory-Compute Macro Using Weight-Feature and Input-Sparsity Aware Schemes for Energy-Efficient Edge AI Devices., , , , , , , , , and 3 other author(s). IEEE J. Solid State Circuits, 59 (1): 219-230 (January 2024)