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Design of a sampling switch for a 0.4-V SAR ADC using a multi-stage charge pump., and . NORCHIP, page 1-4. IEEE, (2014)An ultra-low-voltage OTA in 28 nm UTBB FDSOI CMOS using forward body bias., , and . NORCAS, page 1-4. IEEE, (2015)A 10-bit 50 MS/s SAR ADC in 65 nm CMOS with on-chip reference voltage buffer., and . Integr., (2015)Design of a reference voltage buffer for a 10-bit 1-MS/s SAR ADC., , and . MIXDES, page 185-188. IEEE, (2014)An analog receiver front-end for capacitive body-coupled communication., , and . NORCHIP, page 1-4. IEEE, (2012)A 0.4-V Subnanowatt 8-Bit 1-kS/s SAR ADC in 65-nm CMOS for Wireless Sensor Applications., , and . IEEE Trans. Circuits Syst. II Express Briefs, 63-II (8): 743-747 (2016)Design of a reference voltage buffer for a 10-bit 50 MS/s SAR ADC in 65 nm CMOS., and . ISCAS, page 249-252. IEEE, (2015)Frequency compensation of high-speed, low-voltage CMOS multistage amplifiers., , and . ISCAS, page 381-384. IEEE, (2013)A 12/16 GSps Time-Interleaved Pipelined-SAR ADC with Temperature Robust Performance at 0.75V Supply in 7nm FinFET Technology., , , , , , , , , and 8 other author(s). ESSCIRC, page 333-336. IEEE, (2023)A study on switched-capacitor blocks for reconfigurable ADCs., , and . ICECS, page 649-652. IEEE, (2011)