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Understanding power-performance relationship of energy-efficient modern DRAM devices.

, , , , , and . IISWC, page 110-111. IEEE Computer Society, (2017)

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Defect Analysis and Cost-Effective Resilience Architecture for Future DRAM Devices., , , , , , , , , and 2 other author(s). HPCA, page 61-72. IEEE Computer Society, (2017)Row-buffer decoupling: A case for low-latency DRAM microarchitecture., , , and . ISCA, page 337-348. IEEE Computer Society, (2014)SOUP-N-SALAD: Allocation-Oblivious Access Latency Reduction with Asymmetric DRAM Microarchitectures., , , , , , and . HPCA, page 517-528. IEEE Computer Society, (2017)CiDRA: A cache-inspired DRAM resilience architecture., , , , , and . HPCA, page 502-513. IEEE Computer Society, (2015)Chameleon: Versatile and practical near-DRAM acceleration architecture for large memory systems., , , and . MICRO, page 50:1-50:13. IEEE Computer Society, (2016)Understanding power-performance relationship of energy-efficient modern DRAM devices., , , , , and . IISWC, page 110-111. IEEE Computer Society, (2017)Microbank: Architecting Through-Silicon Interposer-Based Main Memory Systems., , , , , , , and . SC, page 1059-1070. IEEE Computer Society, (2014)GreenDIMM: OS-assisted DRAM Power Management for DRAM with a Sub-array Granularity Power-Down State., , , , , , and . MICRO, page 131-142. ACM, (2021)Reducing memory access latency with asymmetric DRAM bank organizations., , , , and . ISCA, page 380-391. ACM, (2013)Dual-loop 2-step ZQ calibration for dedicated power supply voltage in LPDDR4 SDRAM., , , , , , , , , and 25 other author(s). A-SSCC, page 153-156. IEEE, (2017)