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Joint optimization of speed, accuracy, and energy for embedded image recognition systems.

, , , , and . DATE, page 715-720. IEEE, (2018)

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An efficient parallel motion estimation algorithm and X264 parallelization in CUDA., , and . DASIP, page 91-98. IEEE, (2011)Worst-Case Response Time Analysis of a Synchronous Dataflow Graph in a Multiprocessor System with Real-Time Tasks., and . ACM Trans. Design Autom. Electr. Syst., 22 (2): 36:1-36:26 (2017)Schedule-aware performance estimation of communication architecture for efficient design space exploration., , and . CODES+ISSS, page 195-200. ACM, (2003)SoPloT : service-oriented platform for internet of things: work-in-progress., , , , and . EMSOFT Companion, page 9:1-9:2. ACM, (2017)Software synthesis in the ESL methodology for multicore embedded systems., and . ICSAMOS, page 355-362. IEEE, (2011)A space- and energy-efficient code Compression/Decompression technique for coarse-grained reconfigurable architectures., , , , , , , , and . CGO, page 197-209. ACM, (2017)A Hybrid Performance Analysis Technique for Distributed Real-Time Embedded Systems., , and . CoRR, (2016)Automatic CUDA Code Synthesis Framework for Multicore CPU and GPU Architectures., , and . PPAM (1), volume 7203 of Lecture Notes in Computer Science, page 579-588. Springer, (2011)A Hardware Software Cosimulation Backplane with Automatic Interface Generation., and . ASP-DAC, page 177-182. IEEE, (1998)Pipelined data parallel task mapping/scheduling technique for MPSoC., and . DATE, page 69-74. IEEE, (2009)