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HoLiSwap: Reducing Wire Energy in L1 Caches., , , and . CoRR, (2017)Exploring Modern GPU Memory System Design Challenges through Accurate Modeling., , , and . CoRR, (2018)Energy Efficient On-Demand Dynamic Branch Prediction Models., , , , , and . IEEE Trans. Computers, 69 (3): 453-465 (2020)Hybrid analytical modeling of pending cache hits, data prefetching, and MSHRs., and . ACM Trans. Archit. Code Optim., 8 (3): 10:1-10:28 (2011)CG-OoO: Energy-Efficient Coarse-Grain Out-of-Order Execution Near In-Order Energy with Near Out-of-Order Performance., , and . ACM Trans. Archit. Code Optim., 14 (4): 39:1-39:26 (2017)A Detailed Model for Contemporary GPU Memory Systems., , , and . ISPASS, page 141-142. IEEE, (2019)Kilo TM: Hardware Transactional Memory for GPU Architectures., , , and . IEEE Micro, 32 (3): 7-16 (2012)Cache-Conscious Thread Scheduling for Massively Multithreaded Processors., , and . IEEE Micro, 33 (3): 78-85 (2013)Anticipating and eliminating redundant computations in accelerated sparse training., , , , , and . ISCA, page 536-551. ACM, (2022)Throughput-Effective On-Chip Networks for Manycore Accelerators., , and . MICRO, page 421-432. IEEE Computer Society, (2010)