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Disambiguation of "Chaivipas, Win"

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A Study on Fully Digital Clock Data Recovery Utilizing Time to Digital Converter.

, , and . IEICE Trans. Electron., 90-C (6): 1311-1314 (2007)

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Thein Win

Zaw Win

Win Maung

Thida Win

Sein Win

 

Other publications of authors with the same name

Analysis of CMOS Transconductance Amplifiers for Sampling Mixers., , , and . IEICE Trans. Electron., 91-C (6): 871-878 (2008)Feedforward compensation technique for all digital phase locked loop based synthesizers., , and . ISCAS, IEEE, (2006)A Study on Fully Digital Clock Data Recovery Utilizing Time to Digital Converter., , and . IEICE Trans. Electron., 90-C (6): 1311-1314 (2007)Spatial Sensitivity of Capacitors in Distributed Resonators and Its Application to Fine and Wide Frequency Tuning Digital Controlled Oscillators., , and . IEICE Trans. Electron., 91-C (6): 918-927 (2008)A Low Phase Noise Quadrature Injection Locked Frequency Synthesizer for MM-Wave Applications., , , , , and . IEEE J. Solid State Circuits, 46 (11): 2635-2649 (2011)A 60GHz 16QAM/8PSK/QPSK/BPSK direct-conversion transceiver for IEEE 802.15.3c., , , , , , , , , and 3 other author(s). ISSCC, page 160-162. IEEE, (2011)A 32 Gb/s Data-Interpolator Receiver With Two-Tap DFE Fabricated With 28-nm CMOS Process., , , , , , , , , and 1 other author(s). IEEE J. Solid State Circuits, 48 (12): 3258-3267 (2013)32Gb/s data-interpolator receiver with 2-tap DFE in 28nm CMOS., , , , , , , , , and 1 other author(s). ISSCC, page 36-37. IEEE, (2013)A 56-Gb/s receiver front-end with a CTLE and 1-tap DFE in 20-nm CMOS., , , , , , , , and . VLSIC, page 1-2. IEEE, (2014)A 58-63.6GHz quadrature PLL frequency synthesizer using dual-injection technique., , , , , and . ASP-DAC, page 101-102. IEEE, (2011)