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Shared resource aware scheduling on power-constrained tiled many-core processors., , , , , and . Conf. Computing Frontiers, page 365-368. ACM, (2016)Automatic SMT threading for OpenMP applications on the Intel Xeon Phi co-processor., , , , , and . ROSS@ICS, page 7:1-7:7. ACM, (2014)Accurate memory data flow modeling in statistical simulation., , and . ICS, page 87-96. ACM, (2006)Low-level behavioral analysis of the JVT/AVC decoder., , , , and . VCIP, volume 5308 of SPIE Proceedings, SPIE, (2004)Cole: compiler optimization level exploration., and . CGO, page 165-174. ACM, (2008)Offline Phase Analysis and Optimization for Multi-configuration Processors., , and . SAMOS, volume 3553 of Lecture Notes in Computer Science, page 202-211. Springer, (2005)LA-LLC: Inter-Core Locality-Aware Last-Level Cache to Exploit Many-to-Many Traffic in GPGPUs., , , and . IEEE Comput. Archit. Lett., 16 (1): 42-45 (2017)Restating the Case for Weighted-IPC Metrics to Evaluate Multiprogram Workload Performance., and . IEEE Comput. Archit. Lett., 13 (2): 93-96 (2014)Exploiting program phase behavior for energy reduction on multi-configuration processors., , and . J. Syst. Archit., 53 (8): 489-500 (2007)Sniper: exploring the level of abstraction for scalable and accurate parallel multi-core simulation., , and . SC, page 52:1-52:12. ACM, (2011)