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Combining Symbolic Execution and Path Enumeration in Worst-Case Execution Time Analysis.

, and . WCET, volume 4 of OASIcs, Internationales Begegnungs- und Forschungszentrum fuer Informatik (IBFI), Schloss Dagstuhl, Germany, (2006)

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Predictable bus arbitration schemes for heterogeneous time-critical workloads running on multicore processors., , and . ETFA, page 1-4. IEEE, (2011)Using the abstract interpretation technique for static pointer analysis., , , and . SIGARCH Comput. Archit. News, 27 (1): 47-50 (1999)A Case for Static Branch Prediction in Real-Time Systems., , and . RTCSA, page 33-38. IEEE Computer Society, (2005)Performance of M3S for the SOR algorithm., , and . PARLE, volume 694 of Lecture Notes in Computer Science, page 676-679. Springer, (1993)Predictable Two-Level Bus Arbitration for Heterogeneous Task Sets., , and . ARCS, volume 7767 of Lecture Notes in Computer Science, page 341-351. Springer, (2013)Une approche pour réduire la complexité du flot de contrôle dans les programmes C., , , and . Tech. Sci. Informatiques, 21 (7): 1009-1032 (2002)Multiple-Block Ahead Branch Predictors., , , and . ASPLOS, page 116-127. ACM Press, (1996)An investigation of the performance of various instruction-issue buffer topologies., , and . MICRO, page 279-284. ACM / IEEE Computer Society, (1995)PapaBench: a Free Real-Time Benchmark., , , , and . WCET, volume 4 of OASIcs, Internationales Begegnungs- und Forschungszentrum fuer Informatik (IBFI), Schloss Dagstuhl, Germany, (2006)Exploring Configurations of Functional Units in an Out-of-Order Superscalar Processor., , and . ISCA, page 117-125. ACM, (1995)