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Disambiguation of "Jaussi, James E."

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A 27Gb/s Forwarded-Clock I/O Receiver Using an Injection-Locked LC-DCO in 45nm CMOS.

, , , , , , , , and . ISSCC, page 452-453. IEEE, (2008)

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James E Crouch

James E. Pitkow

Wiebke Jaussi

Michael James

Audrein James

 

Other publications of authors with the same name

A scalable 0.128-to-1Tb/s 0.8-to-2.6pJ/b 64-lane parallel I/O in 32nm CMOS., , , , , , , , , and . ISSCC, page 402-403. IEEE, (2013)A 1.2-5Gb/s 1.4-2pJ/b serial link in 22nm CMOS with a direct data-sequencing blind oversampling CDR., , , , and . VLSIC, page 350-. IEEE, (2015)A 0.5-to-0.75V, 3-to-8 Gbps/lane, 385-to-790 fJ/b, bi-directional, quad-lane forwarded-clock transceiver in 22nm CMOS., , , , , , and . VLSIC, page 346-. IEEE, (2015)A Scalable 32-56 Gb/s 0.56-1.28 pJ/b Voltage-Mode VCSEL-Based Optical Transmitter in 28-nm CMOS., , , , , , , , and . IEEE J. Solid State Circuits, 57 (3): 757-766 (2022)4.5 A 64Gb/s 1.4pJ/b/element 60GHz 2×2-Element Phased-Array Receiver with 8b/symbol Polarization MIMO and Spatial Interference Tolerance., , , , , and . ISSCC, page 84-86. IEEE, (2020)A Low-Power Bidirectional Link With a Direct Data-Sequencing Blind Oversampling CDR., , , , and . IEEE J. Solid State Circuits, 54 (6): 1669-1681 (2019)A 3D-integrated 8λ × 32 Gbps λ Silicon Photonic Microring-based DWDM Transmitter., , , , , , , , , and 4 other author(s). CICC, page 1-2. IEEE, (2023)18.2 A 4x64Gb/s NRZ 1.3pJ/b Co-Packaged and Fiber-Terminated 4-Ch VCSEL-Based Optical Transmitter., , , , , , , , and . ISSCC, page 340-342. IEEE, (2024)Design considerations for low-power receiver front-end in high-speed data links., , , , and . CICC, page 1-8. IEEE, (2013)Strong Injection Locking in Low- Q LC Oscillators: Modeling and Application in a Forwarded-Clock I/O Receiver., , , , , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 56-I (8): 1818-1829 (2009)