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Disambiguation of "Doi, Yoshiyasu"

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A zero-IF 60GHz transceiver in 65nm CMOS with ≫ 3.5Gb/s links.

, , , , , and . CICC, page 471-474. IEEE, (2008)

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Michinobu Doi

Yoshiyasu Takada

Antje Doil

Alfred Doinet

Winfried Döing

 

Other publications of authors with the same name

A 56-Gb/s receiver front-end with a CTLE and 1-tap DFE in 20-nm CMOS., , , , , , , , and . VLSIC, page 1-2. IEEE, (2014)32Gb/s data-interpolator receiver with 2-tap DFE in 28nm CMOS., , , , , , , , , and 1 other author(s). ISSCC, page 36-37. IEEE, (2013)A 60-GHz 1.65mW 25.9% locking range multi-order LC oscillator based injection locked frequency divider in 65nm CMOS., , , , , , and . CICC, page 1-4. IEEE, (2010)A zero-IF 60GHz transceiver in 65nm CMOS with ≫ 3.5Gb/s links., , , , , and . CICC, page 471-474. IEEE, (2008)A 5Gb/s transceiver with an ADC-based feedforward CDR and CMA adaptive equalizer in 65nm CMOS., , , , , , , , , and 5 other author(s). ISSCC, page 168-169. IEEE, (2010)A single-40Gb/s dual-20Gb/s serializer IC with SFI-5.2 interface in 65nm CMOS., , , , , , , , , and 8 other author(s). ISSCC, page 360-361. IEEE, (2009)A 0.8-1.3V 16-channel 2.5Gb/s high-speed serial transceiver in a 90nm standard CMOS process., , , , , , , , , and . CICC, page 131-134. IEEE, (2005)